CMOS VLSI Layout and Verification of a SIMD Computer 1

Psykologi & pedagogik

CMOS VLSI Layout and Verification of a SIMD Computer

Jianqing Zheng • National Aeronautics And Space Administr

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78 sidor
2013

A CMOS VLSI layout and verification of a 3 x 3 processor parallel computer has been completed. The layout was done using the MAGIC tool and the verification using HSPICE. Suggestions for expanding the computer into a million processor network are presented. Many problems that might be encountered when implementing a massively parallel computer are discussed.

Författare: Jianqing Zheng, National Aeronautics And Space Administr
Format: Pocket/Paperback
ISBN: 9781288910304
Språk: Engelska
Antal sidor: 78
Utgivningsdatum: 2013-03-12
Förlag: Biblioscholar