Yield Modelling and Defect Tolerance in VLSI 1
bokomslag Yield Modelling and Defect Tolerance in VLSI
Data & IT

Yield Modelling and Defect Tolerance in VLSI

Will R Moore • Wojciech Maly • Andrzej Strojwas

Inbunden

1429:-

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  • 300 sidor
  • 1988
Papers of the International Workshop on Designing for Yield, Oxford, July 1987. Objectives include discussion of topics in VLSI and designing integrated circuits to yield targets. On yield loss mechanisms and defect tolerance, alternative prospects, catastrophic yield loss models, parametric yield l
  • Författare: Will R Moore, Wojciech Maly, Andrzej Strojwas
  • Format: Inbunden
  • ISBN: 9780852743980
  • Språk: Engelska
  • Antal sidor: 300
  • Utgivningsdatum: 1988-01-01
  • Förlag: Institute of Physics Publishing

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