Hardware Implementation of Current dq PI Controller for FOC PMSM Drive

This book is concentrated on one of the important parts of FOC PMSM drive system: current dq controller, which is usually implemented in DSP based computer. However, these digital solutions are still limited for complex control algorithms and suffer from high implementation cost as well as long execution time. The main challenge for researchers is to reduce the execution time to ensure steadiness of the motor that can be solved by implementing the overall controlling algorithm into FPGA as well as completing the overall execution within limited clock cycles. Altera CycloneTM II EP2C35F67236 FPGA family has been used as target component for the implementation of the proposed current dq PI controller. Verilog HDL coding is used in Quartus II environment for RTL coding while ModelSim SE 6.3a is used to run functional simulations. Agilent 16821A Logic Analyzer is employed to validate the result of the implemented design in FPGA which is connected with the Altera DE2 board through GPIO interfaces. The proposed FPGA based current dq PI controller appreciably outperforms the DSP based solutions at a lower execution time with better accuracy.